Dealing with Own Daughter is an Endless War

                                               

Dealing with daughter

A Data Processing Script for Lucy Li

 1 #!/usr/bin/perl -w
 2 #===============================================================================
 3 #
 4 #         FILE:  processData.pl
 5 #
 6 #        USAGE:  perl processData.pl datafile
 7 #
 8 #  DESCRIPTION:  for Lucy Li. 
 9 #                valid data are those lines with 9 columns
10 #
11 #      OPTIONS:  ---
12 #  ASSUMPTIONS:  1. valid data are those rows with at least 5 columns
13 #                2. all valid data patterns repeat exact the same times
14 #                3. column 5 is the data to be extracted
15 #                4. column 1 and 2 are pattern names
16 #         BUGS:  ---
17 #        NOTES:  ---
18 #       AUTHOR:   Lucy Li
19 #      COMPANY:  
20 #      VERSION:  1.0
21 #      CREATED:  02/03/14 15:36:11 PST
22 #     REVISION:  ---
23 #===============================================================================
24 
25 use strict;
26 use warnings;
27 
28 $, = ",";  #create csv file
29 my $datafile = shift || die "$!\n";
30 my $firstData = 0;   #hold first data pattern
31 my $firstDataFound = 0;  #used for header print
32 my %testData = ();   #hole test data
33 my $headerPrinted = 0;
34 open(DF,$datafile) || die "$!\n";
35  while(){
36   s/"//g;
37   my @data = split(/,/,$_);
38   #ignore those rows first column is not 4 digits
39   if($data[0] =~ m/^\d\d\d\d$/){
40    my $header = $data[0] . "(" . $data[1] . ")";
41    if($firstDataFound == 0 ){
42       $firstData = $data[0];
43       $firstDataFound = 1;
44    }else {
45       if($data[0] eq $firstData){
46           #print header
47        if($headerPrinted ==0){
48         print sort keys(%testData);
49         print "\n";
50         $headerPrinted = 1;
51       }
52        foreach my $value (sort keys(%testData)){
53         print "$testData{$value},";
54        }
55        print "\n";
56       }
57   }
58     $testData{$header} = $data[4];
59   }
60  }
61  foreach my $value (sort keys(%testData)){
62   print "$testData{$value},";
63  }
64  #print values(%testData);
65  print "\n";
66 close(DF);

Install Python Flask

Flask is a small and powerful web framework for Python.


Install virtualenv
Virtualenv is a useful tool that creates isolated Python development environments where you can do all your development work.

sudo apt-get install python-virtualenv
virtualenv flaskapp
cd flaskapp
source bin/activate.csh

Install Flask

pip install Flask

Cadence MTS(Multi-Technology Simulation) Under ADE-L

Goal:
simulating circuits from different technologies when there are library name collisions in addition to model name collisions.

Steps:

1. create netlist (try.scs) with subckt definition in another technology(A):

          example:

             simulator lang=spectre

             // Library name: tcb013ghphvt

            // Cell name: INVHVTD0

            // View name: av_extracted_c

            subckt tsmc13_inv I VDD VSS ZN

               avD1015_1 (ZN I VSS VSS) nch_hvt w=4.3e-07 l=1.3e-07 as=0.2897p \

               ad=0.1462p ps=3.06u pd=1.54u sa=2.4e-07 sb=3.4e-07 nrd=0.790698 \

                  nrs=1.56679 m=(1)*(1)

               avD1323_1 (ZN I VDD VDD) pch_hvt w=6.35e-07 l=1.3e-07 as=0.4004p \

                 ad=0.2159p ps=3.88u pd=1.95u sa=2.4e-07 sb=3.4e-07 nrd=0.535433 \

                  nrs=0.992994 m=(1)*(1)

               c1 (I VDD) capacitor c=8.303e-17

               c2 (ZN VDD) capacitor c=3.085e-17

               c3 (I ZN) capacitor c=1.379e-16

               c4 (I VSS) capacitor c=1.048e-16

               c5 (ZN VSS) capacitor c=3.629e-17

             ends tsmc13_inv

          // End of subcircuit definition.

2.  create an include file(include.scs) including model files and netlist,

     example:

      include "./tsmc13.scs"   section=skew10

      include   "./tsmc13.scs"  section=all_tt

      include "./try.scs"

3. create both schematic and symbol  wrapper for the circuit in technology A, and instantiate the symbol under testbench in technology B

4. in ADE L, setup->Environment, add +mts in userCmdLineOption(still works

without this step)

5. simulation->netlist->recreate

6. goto the netlist directory, add the include file under the subckt

definition in technology A

  example:

  // Library name: rz_tmp

   // Cell name: tsmc13_test

   // View name: schematic

   subckt tsmc13_test ZN I VDD VSS

    include "include.scs"

    I0 (I VDD VSS ZN) tsmc13_inv

   ends tsmc13_test

   // End of subcircuit definition.

7. under netlist directory, run simulation:nc run -D -C mmsim_m -J MTS ./runSimulation

   or hit run in GUI without renetlist.