Netlist Remapping

use the following sample .simrc (placed in project directory) for netlist net name remapping:

vlogifVicSVTextCellViewList = (list "systemVerilogText" "text.v" "VerilogAMSText")
hnlVerilogNetlistBehavioralExplicit = 't
simVerilogNetlistExplicit = 't
;envSetVal("asimenv" "mappingMode" 'string "nmp")   ;default
envSetVal("asimenv" "mappingMode" 'string "oss")
hnlSpectreMapNetInName='("." "\.")
hnlSpectreMapNetInName='((">" "\\>") ("<" "\\<") )

clone HDD - Compressed File Method

(This is copied from https://superuser.com/questions/1097210/clone-only-space-in-use-from-hard-disk)

Compressed file method

To generate the image:

## dd probably needs sudo here.
dd if=/dev/sdb bs=32M | gzip -c > /foo/bar/my_image.dd.gz
To write the image back:

## dd probably needs sudo here.
gzip -cd < /foo/bar/my_image.dd.gz | dd of=/dev/sdb bs=32M
These commands might be built without dd, with gzip only. I used dd to ensure 32 MiB buffer.

Advantages:

The resulting file is non-sparse, it needs no special treatment.
The image size will be reduced even more if the files on your source disk are prone to compression.
Disadvantages:

It is hard to access the files within the compressed image without full decompression (some FUSE may be useful, although I'm not sure, never tried; consider a squashfs approach).

-----------------------
The easiest way, if you use Windows, is to use Paragon Backup & Recovery Free.

1. Backup your original SD card to VM (virtual disk).
2. Restore it to another card, could be a smaller one. The application will ask if the partitions should be shrinked proportionally.

Cadence Schematic/Layout Probe Nets

Ø  Probe nets in both schematic and layout: From schematic window ->Create->Probe -> Add Net (9)

Ø  Save the probed nets in a file: From schematic window ->Create->Probe ->Save

            

Ø  To recover the probed nets in schematic: From schematic window ->Create->Probe ->Load

Ø  To load the probed nets in layout: Select the layout window and type command below in CIW:

geLoadProbe(getCurrentWindow() infile("./probe.out"))

Ø  To delete all the probes in schematic window: Create->Probe->Remove All

Ø  To delete all the probes in layout window: geDeleteAllProbe(getCurrentWindow())