How to Run Cadence QRC with Parasitic Cell Blocking

If you are using the parasitic cell blocking use mode, ie, using the extraction_setup -parasitic_blocking_device_cells_file “hcell_qci” CCL in QRC, please simultaneously make sure that the hierarchy of the cfmom device is preserved during LVS stage. So, if using PVS LVS flow, you need to ensure to run LVS with layout_cell_list and preserve_cell_list. For eg:

layout_cell_list hcell_qci “cfmom*” “cmom*” ind*”

preserve_cell_list hcell_qci

Also, need to ensure to run LVS hierarchically (Eg: use -automatch or Hcell option in PVS). Also, ensure to run LVS with lvs_push_devices_properties yes to ensure no device climbing occurs due to LPE extraction in QRCLVS or RC_DECK On flow.

Determine USB Port in Ubuntu

Method 1: 
ls /dev > notplugged
# plug in device
ls /dev > plugged
diff notplugged plugged

Method 2:
 Run dmesg | grep tty after plugging in your device. The device file should be apparent in one of the lines.

Use this option if the there are floating pins in the schematic that gets dropped in the Extraction

simCheckTermMismatchAction = "ignore"

Send Mail/Attachment From Linux Command Line

%mailx -a  file email_address
Subject: log file
try
.

Install TA-LIB for Python in Ubuntu

Step 1.  Install pip:
  a.  sudo apt-get update

  b. curl "https://bootstrap.pypa.io/get-pip.py" -o "get-pip.py"

  c. sudo python get-pip.py

  d. rehash

Step 2. Install talib for linux:

  a. Download ta-lib-0.4.0-src.tar.gz

  b.  untar and cd to the untared directory

  c. ./configure --prefix=/usr

  d. make

  e.  sudo make install

Step 3.  install necessary python modules:

  a. sudo apt-get install python-dev libxml2-dev libxslt-dev

Step 4. Install TA_LIB Python Wrapper:

a. sudo pip install TA-Lib

Spectre Save Statement

save I1.I2.I3  //--- save all I3 I/O currents
save I1.I2.I3.* // --- save all hierarchical voltages inside I3

two ways to use the save statement, suppose the two lines above are in a file save.scs:
1.  use include in input.scs
    include "/try/save.scs"

2. in ocean:
    definitionFile(
    "/doc/ocean/sim/save.scs"
    )

VerilogIn creates a schematic which has shorted nets

Problem:

When importing a verilog netlist in Virtuoso to create schematic using File->Import->Verilog.  The netlist seems to import successfully, however in schematic, the power nets are shorted

Solution:

On the Verilog In form, in the "Schematic Generation Options" tab enable the option "Minimize Crossovers".   This will relax some of the placement constraints that verilogIn uses to create a schematic. This will give you the correct schematic.