Cadence Automatically Adds Quotation to String Variables in Verilog-A

Problem:

In Cadence Virtuoso 6.1.6-64b, verilog-A instance with string parameters will be quoted in the netlist, this prevents the verilog-A parameters from being treated as variables.

Fig.1 Schematic

Fig.2 Netlist

I97 shows all string parameters are quoted, where I98 is preferred.

Solution:

Change the Base Cell CDF of the Verilog-A cell as shown in Fig.3. Only change those to be used as variables.

Fig. 3 Change CDF Base

After the change of CDF, the parameters can now be used as variables.

Fig.4