VerilogIn creates a schematic which has shorted nets

Problem:

When importing a verilog netlist in Virtuoso to create schematic using File->Import->Verilog.  The netlist seems to import successfully, however in schematic, the power nets are shorted

Solution:

On the Verilog In form, in the "Schematic Generation Options" tab enable the option "Minimize Crossovers".   This will relax some of the placement constraints that verilogIn uses to create a schematic. This will give you the correct schematic.