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Install TA-LIB for Python in Ubuntu

Step 1.  Install pip:
  a.  sudo apt-get update

  b. curl "https://bootstrap.pypa.io/get-pip.py" -o "get-pip.py"

  c. sudo python get-pip.py

  d. rehash

Step 2. Install talib for linux:

  a. Download ta-lib-0.4.0-src.tar.gz

  b.  untar and cd to the untared directory

  c. ./configure --prefix=/usr

  d. make

  e.  sudo make install

Step 3.  install necessary python modules:

  a. sudo apt-get install python-dev libxml2-dev libxslt-dev

Step 4. Install TA_LIB Python Wrapper:

a. sudo pip install TA-Lib

Spectre Save Statement

save I1.I2.I3  //--- save all I3 I/O currents
save I1.I2.I3.* // --- save all hierarchical voltages inside I3

two ways to use the save statement, suppose the two lines above are in a file save.scs:
1.  use include in input.scs
    include "/try/save.scs"

2. in ocean:
    definitionFile(
    "/doc/ocean/sim/save.scs"
    )

VerilogIn creates a schematic which has shorted nets

Problem:

When importing a verilog netlist in Virtuoso to create schematic using File->Import->Verilog.  The netlist seems to import successfully, however in schematic, the power nets are shorted

Solution:

On the Verilog In form, in the "Schematic Generation Options" tab enable the option "Minimize Crossovers".   This will relax some of the placement constraints that verilogIn uses to create a schematic. This will give you the correct schematic.

Cadence doesn't show Cell Name in Symbol

Problem:  New Cadence version doesn't create cell name by any reason as shown below(2nd symbol)

Solution:

Plotting temperature when it is changed as a dynamic transient parameter

The simulation temperature is changed during a transient analysis, by making it a  dynamic parameter. For example: tran tran stop=20n errpreset=conservative write="spectre.ic" \     writefinal="spectre.fc" annotate=status maxiters=5 \     param=temp param_vec=[0 120 1u 170] param_step=1m This will change the simulation temperature from 120 degrees at time=0, to 170  degrees at time=1us. How can the temperature be plotted as a function of time?

Add this line to a file which is included in the netlist: save temp When using ADE, type "save temp" in a new file with .scs extension such as   "include.scs".  Then add the file in Setup - Model Libraries. The "temp" variable  will then be available for plotting in the Results Browser.

Cadence Automatically Adds Quotation to String Variables in Verilog-A

Problem:

In Cadence Virtuoso 6.1.6-64b, verilog-A instance with string parameters will be quoted in the netlist, this prevents the verilog-A parameters from being treated as variables.

Fig.1 Schematic

Fig.2 Netlist

I97 shows all string parameters are quoted, where I98 is preferred.

Solution:

Change the Base Cell CDF of the Verilog-A cell as shown in Fig.3. Only change those to be used as variables.

Fig. 3 Change CDF Base

After the change of CDF, the parameters can now be used as variables.

Fig.4

Which one is faster, eSATA, USB or SD?

I am always curious on the speed map of the same media using different interfaces. Finally I did a test with the results shown. Surprisingly, HDD shows better overall speed, even when used as USB2 device, and SD doesn't show  better speed over USB.

Wind Turbine Hybrid System Test Report

Test Report for Wind Turbine Hybrid System